Abstract
AbstractAs the degree of integration increases and the power supply voltages decrease in MOS dynamic RAM's, soft errors become increasingly important and need to be studied from the points of view of circuit, process and device technology. In this paper, analytical and experimental studies are conducted on the soft errors of 64‐Kbit dynamic RAM's. First, the relation between the device parameters and the critical charge is examined. If the charge distribution collected in the silicon substrate is Gaussian, the soft error rate is expressed as a complementary error function of the critical charge and agrees well with the experimental results conducted by the use of 241 Am. To improve the soft error, we studied the use of Hi‐C cell structures for increased critical charges and reduced charge collection area by employing polysilicon bit lines and boosted word lines before operation of the sense amplifier. Compared with conventional structures, the critical charge is increased 1.8 times and the collection area reduced to less than half. As a result, the soft error is improved by 700 times and the chip itself is less susceptible to soft error.
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