SoC-level risk assessment using FMEA approach in system design with SystemC

Abstract

As system-on-chip (SoC) becomes prevalent in the intelligent system applications, the reliability issue of SoC is getting more attention in the design industry due to the rapid increasing rate of radiation-induced soft errors while the SoC fabrication enters the very deep submicron technology. Therefore, the SoC dependability becomes a critical issue in safety-critical applications. Validating such systems is imperative to guarantee the dependability of the systems before they are being put to use. Moreover, it is beneficial to assess the SoC robustness in early design phase in order to significantly reduce the cost and time of re-design. To fill such needs, in this study, we propose a useful IP-based SoC-level risk model using failure mode and effects analysis (FMEA) method to assess the robustness of a SoC in SystemC transaction-level modeling (TLM) design level. The proposed risk model is able to facilitate the measure of the robustness and scales of failure-induced risks in a system, which can be used to identify the critical components and major failure modes for protection so as to effectively reduce the impact of failures to the system. A case study is used to demonstrate our risk model under CoWare Platform Architect environment. A system verification tool was created to assist us in measuring the robustness of the system, in locating the weaknesses of the system, and in understanding the effect of faults on system failure behavior during the SoC design phase. The contribution of this work is to promote the dependability verification to TLM abstraction level that can significantly enhance the simulation performance, and provide the comprehensive results to validate the system dependability in early design phase for safety-critical applications.