Slewer fractional-order-hold: the ideal DAC response for direct digital synthesizers

Abstract

Digital-to-analog converters (DACs) are the principal performance limiting components in the sine output direct digital synthesizers (DDSs). This paper presents a novel DAC response called Slewer Fractional-Order-Hold or just Fractional-Order-Hold (/spl Delta/OH) which is designed to optimize DAC performance in DDSs. This Fractional-Order-Hold response also applies to Sample-and-Hold (S&H) output waveforms where the S&H follows a DAC. The conventional DAC response modeled with the Zero-Order-Hold (ZOH) response may be largely responsible for the shortcomings of DAC specifications for the DDS application where low spurs are desired. Conventional definitions of differential and integral nonlinearity (DNL and INL) are only applicable to the settled state, and glitch area and settling time specifications for the transient are inadequate when spurs are a concern. First, this paper discusses how the dynamic linearity, glitch area, and other DAC response parameters affect spur levels in a DDS. Second, this paper describes the novel /spl Delta/OH response and compares its performance to that of other conventional responses such as the ZOH. Finally, this paper discusses a newly patented DAC design, the Smooth Transition Digital-to-Analog Converter (STDAC), which strives to implement the /spl Delta/OH response. The STDAC improves on prior art by applying the /spl Delta/OH that rigorously defines how the waveform should dynamically make the transitions, from one settled output level to another, optimizing these transitions to minimize DAC spurs.