Abstract
Running clock synchronization protocols over packet based networks introduces a considerable challenge, since clock accuracy is highly sensitive to the network latency behavior. As packet based networks are becoming the common transport for most applications requiring clock synchronization, accuracy requirements are becoming increasingly stringent. In this paper we introduce a novel approach that uses multiple communication paths between the master and slave clocks to improve the clock accuracy without increasing the total rate of protocol messages. We show that the multi-path approach can also be used to reduce the time error caused by asymmetric communication paths. We present simulation results that demonstrate the effectiveness of our approach.
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