Single-Poly-EEPROM Cell in Standard CMOS Process for Medium-Density Applications

Abstract

A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling device is used for programming and erasing, and an nMOS transistor is used for reading and selecting the memory cell when it is in an array. The pMOS device is a minimum-sized digital transistor with the gate oxide of the input/output transistors. This improves the coupling capacitance, minimizes the area consumption, and guarantees the retention. The memory cell is programmed by band-to-band hot electrons and erased by Fowler–Nordheim tunneling. Thanks to the proposed writing scheme, the memory cell requires only a single triple-well. This further reduces the area consumption, and ensures, at the same time, fast and reliable memory operations. The measurements on programming, erasing, reading, cycling endurance, and data retention are provided using a 0.18- $\mu \text{m}$ standard CMOS process. The memory cell area is 5.91 $\mu \text{m}^{2}\vphantom {\sum ^{R^{r}}}$ in an array, and it can be programmed in $t_{P}=1$ ms, erased in $t_{E}=10$ ms, and cycled for >10k times with a voltage window greater than 2 V.