Single step lithography for double-recessed gate pseudomorphic high electron mobility transistors

Abstract

An asymmetric double-recessed gate process achieved through a single lithography step and a combination of wet and dry etching techniques is presented. The double-recessed gate process is beneficial in the fabrication of InGaAs/AlGaAs/GaAs pseudomorphic high electron mobility transistors (PHEMTs) because breakdown voltage is enhanced while surface effects on the drain side of the gate are minimized. In contrast to conventional processes that require two lithography steps, the current process requires only a single lithography step for the asymmetric placement of a T-gate in a wide recess trench. The process utilizes a four-layer resist of polymethylmethacrylate (PMMA) and P(MMA-MAA) exposed by electron beam lithography. Upon development of the resist, a wet selective etch (citric acid:H2O2) is used to define the wide recess trench and then a dry selective etch (SiCl4/SiF4) is used to recess a narrow trench (within the wide recess trench) in which the gate foot rests. This technique can achieve gate lengths of 0.15μm and drain-side wide recess dimensions from 0.15 to 0.55μm while the source-side recess width is kept at or below 0.15 μm. Device results show improved breakdown voltages and output conductance with only slight reduction in transconductance and drain current for the PHEMTs fabricated using the technique as compared to PHEMTs fabricated using a trilayer T-gate process.