Abstract
Heavy ion and proton single event upsets of 4 M SOI SRAM with a hardened delay element in each memory cell were evaluated. These 4 M SRAM were fabricated in UNIBOND substrates using a radiation hardened partially depleted silicon-on-insulator CMOS technology. Limiting heavy ion upset cross-section of 1.2/spl times/10/sup -10/ cm/sup 2//bit has been achieved. Limiting proton upset cross-section of 1.1/spl times/10/sup -17/ cm/sup 2//bit has also been obtained.
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