Simulations of passively enhanced conjugate heat transfer across an array of volumetric heat sources

Abstract

Numerical simulations were performed to investigate convective–conductive heat transfer due to a laminar boundary layer flow of air over a two dimensional array of rectangular chip blocks which represent the finite heat sources. The main focus of this study is on the simulation of the flow fields and temperature variations of the air and the chip blocks. The purpose of this study is to verify the effects of the openings of the board in the areas between the chip blocks on the enhancement of cooling the heating blocks. Due to a pressure differential occurring across the opening, the induced vertical flow serves as a suction or blowing force and consequently enhances heat dissipation to the ambient fluid. The optimal configuration of the chip board regarding cooling the heat source would yield lower chip temperatures with limited chip-to-chip temperature variations. A time-accurate numerical scheme algorithm, PISO (pressure-implicit with splitting of operators), is used to simulate the conjugate heat transfer between the fluid and solid phases. In this work, a set of false solid properties was employed to force the solid side to have a time scale comparable to that of the fluid side in order to avoid numerical instabilities due to different time scales used in the calculations. The results of the simulations show that the existence of the array of blocks results in stagnant flow regions between blocks in which heat convected to the ambient flow field is limited. It was found that heat transfer can be enhanced passively, especially in the areas between blocks, by opening the chip board between blocks. The enhancement of heat transfer thus occurring is presumably due to a pseudo-suction force which induces a vertical flow between blocks. The enhancement of heat transfer for the chips on-board is reflected by a global increase of the Nusselt number on the chip blocks, especially on the west sides of the chips located further downstream of the flow direction. Further investigation shows that the chip-to-chip temperature variations diminish if the openings located upstream of the front end block and downstream of the rear end block are sealed. The optimal cooling configuration for the array of chip blocks can be utilized by the electronics industry. © 1997 John Wiley & Sons, Ltd.