Abstract
In this paper we propose an analytical approach to investigate the electrostatic impact of very small charged regions in the gate dielectric of dual bit non-volatile memories (NVMs) Silicon-On-Insulator (SOI) cells. This original model is based on the surface potential approach and allows to investigate the behavior of NVMs in subthreshold working condition. It is particularly accurate for charged region, as small as L 2 = 10 nm and up to a charge density of Q = 1013 cm−2 and it is complementarity to another approach proposed for bulk devices [1]. Relevant consequences of the asymmetric charging of the storage layer on the electrical characteristics of discrete-trap memories are thoroughly analyzed: the importance of Short Channel Effects (SCEs) for the performance of these cells is highlighted. Moreover a method for extracting an “effective” distribution of charges from the transfer characteristics is derived.
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