Abstract
The needs of modern life are driving high powered CPU and SoC devices into harsh environments. The physical design changes required to meet these use case conditions negatively impact the signal and power integrity performance, limiting the speeds and capabilities that are achievable. The signal and power integrity desires directly oppose one another, so a holistic platform design approach is required to optimize system performance. This paper investigates the LPDDR4 challenges faced and results obtained by the signal and power integrity design teams as they worked together to provide an optimal, balanced design that would meet the customer requirements.
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