Abstract
Precise placement of twin boundaries and stacking faults promises new opportunities to fundamentally manipulate the optical, electrical, and thermal properties of semiconductor nanowires. Here we report on the appearance of consecutive twin boundaries in Si nanowires and show that sidewall morphology governs their spacing. Detailed electron microscopy analysis reveals that thin {111} sidewall facets, which elongate following the first twin boundary (TB1), are responsible for deforming the triple-phase line and favoring the formation of the second twin boundary (TB2). While multiple, geometrically correlated defect planes are known in group III-V nanowires, our findings show that this behavior is also possible in group IV materials.
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