Short-Channel Performance Improvement by Raised Source/Drain Extensions With Thin Spacers in Trigate Silicon Nanowire MOSFETs

Abstract

We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width (W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NW</sub> ) down to 10 nm. We found that the parasitic resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> ) of nanowire transistors is dominated by nanowire-shaped source/drain (S/D) regions under the gate spacer whose resistivity is higher than that in wider regions. We succeeded in significant reduction by raised S/D with thin gate spacer whose width is 10 nm. Although the parasitic capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">para</sub> ) increases by spacer thinning, C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">para</sub> increase is much smaller than R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> reduction, and great performance improvement is obtained for a W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NW</sub> of less than 15 nm.