Short tests for contact circuits with similar-type weakly connected faults of contacts

Specific physical defects of high performance circuits manifest themselves as path delay faults (PDFs). A pair (v1, v2) of test patterns is required to detect a PDF. A PDF is robust testable if there is a test pair on which the fault manifestation does not depend on delays of other circuit paths. A PDF is non robust testable if manifestation of the fault on any test pair is possible only when all other paths of the circuit are fault free. For high quality delay testing it is desirable to detect delay of any path regardless of delays of other paths. In this paper, synthesis of a circuit by covering each nonterminal node of the reduced ordered binary decision diagram (ROBDD) or free binary decision diagram (Free BDD) system with the original subcircuit from gates is suggested. Delay testability of such circuits is investigated. It is specified that the PDF of each path of the circuit is detected without injecting additional inputs into the circuit. It is well known that the BDD is a directed acyclic graph based on the Shannon decomposition in each nonterminal node v: 0 1 i i x x v i v i v f x f x f = = = ∨ . Here fv is the function corresponding to the node v, and the decomposition variable xi marks the node v. The dashed edge drops in the node corresponding to the function 0 i x v f = , and the bold edge drops in the node corresponding to the function 1 i x v f = . The BDD is called ordered (OBDD) if variables are encountered in the same order in all paths connecting the BDD root with the terminal node. The BDD is called reduced (RBDD) if it does not contain either isomorphic subgraphs or nonterminal nodes such that 0 1 i i x x v v f f = = = . An example of reduced and ordered BDD (ROBDD) is shown in Fig. 1. When deriving the Free BDD, a suitable decomposition variable is chosen for each nonterminal node v independently of other nonterminal nodes. That may cut the number of Free BDD of nonterminal nodes in comparison with the ROBDD (for the same function). Let 1 { ,..., } m F f f = be a system of Boolean functions describing combinational circuit behavior. Derive the ROBDD using the same order of variables for each Boolean function from F. Join isomorphic subgraphs in different ROBDDs. Combine different ROBDDs of 1-terminal nodes into one 1-terminal node and their 0-terminal nodes into one 0-terminal node. As a result, we obtain the graph with m roots and two terminal nodes. This graph represents a system of m Boolean functions. It is called the shared ROBDD. Without loss of generality, we will further consider systems with one function as an example. In Fig. 1, the ROBDD for one Boolean function is shown. The ROBDD represents the disjoint sum of products (DSoP) of the function f as follows:

In a recent paper, Jain et al. [1992] probabilistically establish the equivalence of two given Boolean functions. They assign randomly selected integers to input variables and compute integer-valued transform functions. If the evaluations give the same value, the Boolean functions are shown to be identical with some probability of error, The error probability is reduced as the domain from which the integers are obtained is enlarged. Also, for a fixed domain, the probability of error can be reduced by taking multiple samples for inputs. In this paper, we assign randomly selected real numbers to input variables and show that when the characteristic polynomials of two Boolean functions give the same value, then the functions are identical with probability 1. It can be shown that when the inputs are sampled from the real domain [0,1], and are interpreted as probabilities of logic 1, then the corresponding value of the characteristic polynomial gives the probability of output logic 1 for the Boolean function.

Derivative operations of the Boolean differential calculus are very useful for many applications, like the test of digital circuits, the synthesis using the bi-decomposition of Boolean functions, the specification of Boolean functions with regard to certain properties, etc. Basically, a derivative operation can be executed for a single Boolean function. Here we extend the known theory such that each of the ten derivative operations can be applied to classes \(\mathcal {C}_N\) of Boolean functions without the need to compute the derivative operation for each Boolean function of the class separately.

In this paper, we discuss the application of byte error detecting codes to the design of self-checking circuits for the single stuck-at fault model. We discuss strongly fault-secure realization of a given Boolean function using byte error detecting codes. Even though parity is the most efficient separable code for the detection of single errors, we show that the use of a byte error detecting code can lead to lower cost of self-checking realization of a given function as compared to its self-checking realization using the parity code. We also present a method for the design of totally self-checking checkers for byte error detecting codes. Experimental results obtained for various test circuits are also discussed. >

Application of byte error detecting codes to the design of self-checking circuits

Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor ( nu MOS), a single MOS transistor simulating the function of biological neurons. To facilitate logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage nu MOS inverters. One of the most striking features of nu MOS binary-logic application is the realization of a so-called soft hardware logic circuit. The circuit can be made to represent any logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified. >

Techniques for deriving the minimum length tests are developed for irredundant combinational circuits that contain single faults. The development is based on the Boolean difference function. The Boolean difference function is expanded to form two analytical expressions that can be used to calculate the tests for any stuck-at-zero and stuck-at-one fault within combinational circuits.

The authors propose a new method for testing logic circuits, termed balance testing, which requires no explicit signatures and is particularly attractive for built-in self-testing. It exploits the balance property possessed by many useful Boolean functions: f(X) is balanced if f(X) = 1 for half its input combinations. The authors analyze balance testing by deriving necessary and sufficient conditions for the detectability of single stuck-line, multiple stuck-line, and bridging faults. These conditions help the designer identify individual faults that remain undetected by balance testing. The analysis also obviates the need for error models that are often difficult to validate. Some feasible design techniques to make logic circuits balance testable are demonstrated.

The full diagnostic test for contact circuits in the presence of one-type contact faults (breaking or closure) is considered. We constructively establish that any Boolean function can be realized by a contact circuit permitting a non-trivial full diagnostic test, i.e., a test containing not all input vectors.

The cost of design, test and fabrication of self-timed circuits remains prohibitive for their wider adoption in practice. Addressing this issue, researchers are trying to find ways for rapid prototyping of self-timed circuits in FPGAs. Combinational logic is realized in FPGAs by look-up tables (LUTs), which are typically built as a binary tree of 2-way multiplexers (MUX 2:1). This brings us to the idea of using MUX 2:1 in self-timed designs particularly, in quasi-delay-insensitive (QDI) circuits. Multiplexers however, realize a binate (non-monotone) Boolean function and therefore may cause logic hazards. A standard way for preventing these hazards requires designing of special circuit for MUX 2:1. On the other hand, there are indirect evidences that the multiplexers in some commercial FPGAs are hazard-free. Based on this assumption, we propose an original approach for realizing a multi-input C-element, which is widely used in QDI circuits. This paves the way for using hazard-free MUX 2:1 in more complex self-timed elements. All the proposed circuits are designed and verified in a CAD tool Workcraft.

The KR realization (see S. Kundu and S.M. Reddy, Proc. 18th Int. Fault-Tolerant Computing Symp., p.220-25 1988) was proposed with the aim of designing testable CMOS combinational circuits using only primitive gates and no extraneous hardware. It is shown that for some useful Boolean functions the size of the KR realization is exponential in the number of input variables. The author presents a testable realization of a CMOS combinational circuit, with respect to FET (field-effect-transistor) stuck-open faults, named FM-CMOS. It uses only two-input multiplexers and, to an extent, addresses the size-problem of the KR realization. More specifically, it is shown that for some useful Boolean functions for which the size of the KR realization is exponential in the number of input variables the size of the FM-CMOS realization is polynomial in the number of input variables. For this reason, it is proposed that the FM-CMOS realization be used in conjunction with the KR realization. The results are applied to design a testable n-b CMOS adder that uses only O(n) FETs. >

Cause-Effect Chains Analysis (CECA) usually results in a diagram showing particular effects with arrows denoting causality and logical operators, reflecting interrelation between causes implying particular effects. Intended outcome of the analysis is to identify main causes triggering observed surface problems. From this point of view the resulting model may be considered a set of functions interrelating occurrence of key disadvantages and initial / target disadvantages. This paper describes the concept of modelling Cause-Effect Chains with Boolean functions. Such approach allows for direct application of techniques used in the area of digital circuits design and testing. Provided examples demonstrate how the proposed logical model may support decisions regarding changes in the analysed technical system.

Approximate evaluations of characteristic polynomials of Boolean functions

The continuous effort how to achieve space-efficient implementation of a digital circuits may soon arrive at the physical limits behind the scaling of fundamental building components. One possible response to this problem can be recognized in adoption of so called multifunctional logic, which also comes with the intrinsically embedded reconfiguration features. Polymorphic electronics concept with its substantial technological independence opens a way to fulfil this objective through the adoption of emerging semiconductor technologies and advanced synthesis methods. This paper is dealing with a proposal of a novel synthesis method oriented on the exploitation of polymorphic electronics principles. Key part of it is based on Boolean divisor identification and function kernelling technique. Proposed method is evaluated with several test circuits.

We consider combination circuit C and some its nodes that faults are detected on the last stages of circuit fabrication. Besides, injections of Trojan Circuits (TCs) in certain circuit C lines may be also detected. (It is assumed that TC payload output is inserted into a line of a combinational circuit). In both cases circuit C improper functions are changed for incompletely specified Boolean functions correlated with the corresponding fault nodes or the circuit lines of correct circuit C. That is why masking of circuit faults and TCs injections may be reduced to implementation of a patch circuit that realizes the correct system of incompletely specified Boolean functions, in particular, depending on internal circuit C variables. The correct system is calculated with using SAT solver. Patch circuit inputs are connected with internal nodes of circuit C that precede both fault nodes and the lines. Patch circuit outputs are connected with nodes that are fed either by fault nodes or by circuit lines in which Trojan circuits are inserted. Experimental results are executed on ISCAS test circuits. The results show that patch circuits as a rule are simpler than duplication subcircuit with fault node as outputs and preceding nodes as inputs.