Short channel effects in double gate polycrystalline silicon SLS ELA TFTs

Abstract

Short channel effects in double gate poly-Si SLS ELA TFTs are studied in this work by electrically characterizing devices with varying top gate length and constant bottom gate length. The electrical parameters were extracted for different bottom gate biases, observing a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> increase with increasing channel length, attributed to more traps present within larger channels. This was also probed through the increase of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g,max</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> with increasing channel length. In order to distinguish between short channel effects and possible L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">top</sub> /L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bottom</sub> effects, devices with different bottom gate lengths and a constant top gate length were also studied. No similar trends as in the case of decreasing channel length were observed, thus supporting our case that the previously observed behavior is mainly an effect of channel shrinking and not of L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">top</sub> /L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bottom</sub> effects.