SEU Fault Tolerance of FPGA with Multi-Bits Input for Satellite

Abstract

A single event upset (SEU) is a change of state caused by ions or electro-magnetic radiation striking a sensitive node in a micro-electronic device, such as in a micro processor, semiconductor memory, or power transistors. This paper describes advanced methods and design concepts to make fault tolerant to SEU for programmable architectures, the wellknown Filed Programmable Gate Array (FPGAs). FPGAs are becoming more valuable for space applications because of their high density, high performance, reduced development cost and re-programmability. There are many approaches to mitigate SEU fault using FRPA. Among these, we propose VHDL-based approach using time redundancy and hardware redundancy. This approach is expected to detect and mitigate SEU fault. Also the location that SEU occurred can be detected. The presented method is verified by simulation using Xilinx ISE tool. Especially, the fault tolerant method for multi bits input of FPGA is proposed in this paper. Futhermore, a FPGA hardware systems are presented to evaluate the performance of algorithm.