Abstract
This paper presents a new control strategy for reducing the switching losses produced by the use of high parasitic capacitance solar arrays in the sequential switching shunt regulator. Instead of dividing the solar array into equal sections, the proposed strategy is based on two different sections types, low-capacitance and high-capacitance ones. In order to reduce the switching losses and to maintain the original closed-loop response, a novel parallel power processing control strategy is implemented. With this new technique the low-capacitance sections are the only ones that switch at high frequency to regulate the bus while the high-capacitance sections are only connected or disconnected under high load power changes. In addition, the control closed loop delay associated to the time needed to charge the parasitic capacitance has been modelled and a controller modification is proposed to reduce AC performance degradation.
Highlights
In European high-power telecommunication satellites, the regulated power bus is the most used power bus architecture [1]
A 60◦ phase margin (PM) and 10 dB gain margin (GM) for begin-of-life conditions are imposed in order to assure the accomplishment of the standard PM and GM for worst case end-of-life conditions
E4351B Solar Array Simulators from Keysight Technologies was used as inputs for the prototype while the load has been emulated with a DC Electronic Load N3300 from Keysight
Summary
In European high-power telecommunication satellites, the regulated power bus is the most used power bus architecture [1]. The benefit of having smaller sections is the reduction of the CSA , which combined with an increase of the CBUS , reduces the switching frequency and improves the AC characteristics of the system These solutions have a constraint at system level; a high number of sections or a higher CBUS penalize the system in terms of mass and volume. Another proposed solution to reduce the switching frequency is the use of nesting on the S3 R cells [10], but with the penalty of making the transconductance gain depend on the regulator operating point and complicating the control loop design. This control loop is modeled and simulated, improving the AC behavior of the regulator
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
