Sequential, Irregular and Complex Object Contour Tracing on FPGA

Abstract

This paper proposes a real-time, robust, scalable and compact field programmable gate array (FPGA) based architecture and its implementation of contour tracing of video objects. Achieving realtime performance on general purpose sequential processors is difficult due to the heavy computational and memory access demands in contour tracing, thus a hardware acceleration is inevitable. Our finding to the existing related work confirms that the proposed architecture is much more feasible, cost effective and features important algorithmic-specific qualities, including deleting dead contour branches and removing noisy contours, which are required in many video processing applications. Our implementation achieved an optimum processing clock of 158 MHz while utilizing minimal hardware resources and power. The proposed FPGA design was successfully simulated, synthesized and verified for its functionality, accuracy and performance on an actual hardware platform which consists of a frame grabber with a user programmable Xilinx Virtex-4 SX35 FPGA.