SENSE: Sketching Framework for Big Data Acceleration on Low Power Embedded Cores

Abstract

Ever-growing IoT demands big data processing and cognitive computing on mobile and battery operated devices. However, big data processing on low power embedded cores is challenging due to their limited communication bandwidth and on-chip storage. Additionally, IoT and cloud-based computing demand low overhead security kernel to avoid data breaches. In this chapter, we present, “SENSE”, Sketching and Encryption on Scalable heterogeneous Engine for data reduction and encryption. SENSE is a heterogeneous framework which consists of three important kernels: 1. sketching module for data reduction, 2. an accelerator for efficient sketch recovery using scalable and parallel reconstruction architecture and 3. a host processor to perform post processing. SENSE framework can reduce data up to 67% with 3.81 dB signal-to-reconstruction error rate (SRER). One of the critical challenges in big data processing on embedded hardware platforms is to reconstruct the sketched data in real-time with stringent constraints on error bounds and hardware resources. We explore Orthogonal Matching Pursuit (OMP) algorithm for sketch data recovery. OMP is a greedy algorithm with high computational complexity which has emerged as an important tool for signal recovery, dictionary learning and sparse data classification. We use a domain specific many-core hardware named Power Efficient Nano Cluster (PENC) designed by EEHPC lab at University of Maryland, Baltimore County. To demonstrate efficiency of SENSE framework, we integrate it with Hadoop MapReduce platform for face detection application. The full hardware integration consists of tiny ARM cores which perform task scheduling and application processing, while PENC acts as an accelerator for sketch reconstruction. We show performance of SENSE framework on face identification application.