Abstract
Self-align nitride (SAN) logic NVM cell has been successfully demonstrated in 28nm CMOS technology with high-k gate dielectric layer and metal gate WL for coupling. This work proposed a new method for program and erase of the SAN cells, when gate length and gate spacing scales aggressively to 40nm and 70nm, respectively. Reliable 2-bit per cell operation by local hot hole injection controlled by metal gate WLs are demonstrated successfully for future applications of high density logic NVM arrays.
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