Self-Reconfigurable Channel Data Buffering Scheme and Circuit Design for Adaptive Flow Control in Power-Efficient Network-on-Chips

Abstract

This paper presents a self-reconfigurable channel data buffering scheme and circuit design for next-generation network-on-chips (NoCs). The design is optimized for power efficiency and data throughput, from system to circuit level. During network congestion, the buffering scheme realizes adaptive flow control by reconfiguring the channel buffers for online data storage. Once congestion is alleviated, data transmission resumes from the foremost buffer stage, thereby improving NoC throughput. It also achieves system-level power optimization through an integrated hardware-software codesign approach. Using software techniques such as dynamic voltage and frequency scaling, optimal voltages and frequencies are provided to the system through a hardware-based single-inductor multiple-output dc-dc converter platform. Meanwhile, power dissipation is further minimized through switched-capacitor delay control modules. A CMOS IC prototype has been fabricated, with 16-bit data transmission capability. It demonstrates 58.9% power saving over conventional designs. To achieve the same throughput, it consumes only 45.4% power of the best prior art. The flexibility of the buffering scheme, along with the integrated power management solution, allows it to be applied to most existing commercial NoC architectures.