Self-heating-aware cell design for p/n-vertically-integrated nanowire on FinFET beyond 3 nm technology node

Abstract

Self-heating-aware design for p/n-vertically-integrated nanowire (NW) on FinFET is investigated for beyond 3 nm technology node. The practical fabrication process architecture for nanowires on FinFET has been also proposed. Based on the assumptions of process flow, cell layouts for inverter, transmission gate, NAND, NOR and 6T-SRAM are designed. Consequently, remarkable area reductions are achieved for various CMOS circuits including multi-stacked circuits resulting in the suppression of the self-heating effect simultaneously.