Influence of Gate Dimensions on High Power Microwave Injection Effects for AlGaAs / GaAs pHEMT

With the development of microelectronic technology, the reliability of devices in a complex electromagnetic environment has become one of the greatest challenges in the semiconductor industry. On this basis, a phenomenon of nonlinear transient response is observed in high-power microwave (HPM)-radiating AlGaAs/InGaAs pseudomorphic high-electron-mobility transistors (pHEMTs). This abnormal response is induced before the thermal failure, causing disturbances to the circuit. To understand this phenomenon, a detailed mechanism analysis is proposed. The analysis shows that the nonlinear response is initially associated with the 2DEG velocity saturation, then a breakdown process is induced by the tunneling and impact ionization combined effect. Within each radiation period, the channel current changes its direction twice under the influence of the HPM field. The nonlinear response current $I_{d}$ is derived from the theoretical analysis. TCAD simulations demonstrate the saturation and breakdown process. Corresponding experiments are performed using a Ka-band low-noise amplifier (LNA) chip. The results support the theory well.

Superconducting Generators: Enabling Airborne Directed Energy Weapons

Study on high power microwave nonlinear effects and degradation characteristics of C-band low noise amplifier

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (Vt), Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the Ioff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

This paper presents the effects of process parameters variations of new underlap SOI MOSFETs (underlap SOI technology with spacer covered) on linearity investigation of cascode low noise amplifier (LNA) for wireless LAN application. By quantifying the linearity of the LNA in-terms of third order intercept (IP3), the paper presents guidelines for optimum value of spacer s, film thickness TSi doping gradient d and gate length LG of the underlap device for linearity enhancement of the LNA. Based on a new Figure-of-Merit of LNA (FoMLNA) involving available signal power gain G, IP3, noise figure (NF) and dc power consumption Pdc, it has been found that FoMLNA in double gate (DG) configuration is much higher than single gate (SG) one at the optimum gate overdrive VOD = 75 mV. This is due to a combined effect of higher value of G and IP3 in the DG configuration. By comparing with limited available experimental data of 0.18 μm bulk technology, it has been found that using new underlap SOI MOSFETs with gate length of LG = 60 nm (effective gate length Leff = 92 nm) optimally designed and optimally biased LNA gives almost two times improvement in the proposed FoMLNA. With optimal bias the LNA achieved the following indicators: NF ~ 2.27 dB, IP3 ~ +7.75 dBm, G ~ 20.86 dB and power consumption equal to 2.5 mW.

In this paper, the damage process and mechanism of the typical high electron mobility transistor by injecting high power microwave signals are studied by simulation and experiment methods. By using the device simulator software Sentaurus-TCAD, a typical two-dimensional electro-thermal model of high electron mobility transistor is established with considering the high-field saturation mobility, Shockley-Read-Hall generation-recombination and avalanche breakdown. The simulation is carried out by injecting the 14.9 GHz, 20 V equivalent voltage signals into the gate electrode. Then, the distributions of the space charge density, electric field, current density and temperature with time are analyzed. During the positive half cycle, a conduction channel appears beneath the gate electrode near the source side within device. It is found that the electric field is extremely strong and the current density is very large. Therefore, the temperature increases mainly occurs beneath the gate electrode near the source side. During the negative half cycle, because of the concentration of the large number of carriers induced by avalanche breakdown, the electric field is stronger than that in the positive half cycle. But the current density is lower than that in positive half cycle. Therefore, the increase of temperature is dominated by the electric field. With the effects of both strong electric field and high current density, the temperature of the transistor rises in the whole signal cycle. In addition, temperature in the positive half-cycle rises faster than that in the negative half-cycle.Furthermore, the peak temperature appears at the location beneath gate electrode near the source side because the electric field and current density are strongest in this area. When the temperature within the device is higher than 750 K, intrinsic breakdown occurs in GaAs material, so the heating process becomes quicker. With the temperature increases, the GaAs reaches its melting point, and the device fails permanently. Furthermore, taking the original phase of 0 and for example, we discuss the influences of different original phases on damage process. It is shown that when original phase is zero, the temperature increase rate is faster, and the burn-out time is shorter.Failure analysis of high electron mobility transistor devices damaged by microwaves is carried out with scanning electron microscope, and the simulation results are well consistent with the experimental results. The conclusion may provide guidance for studying high power microwave defense of low noise amplifier and rugged design of high electron mobility transistor in fabrication technology.

The reliability of electronic device is threatened in high power microwave (HPM) environment. In accordance with the situation that the emulation is ineffective in evaluating the accuracy and precision of the HPM effect to electronic device, the experimental method is used to resolve the problem. Low Noise Amplifier (LNA) and Limiter are selected as the objects for the experiments, the structural characteristic of the front-end of radar receiver is described, the phenomena and criterion are elaborated and analyzed using injection method due to its ability to get an accurate threshold avoiding the complex coupling, the basic principle of injection experiment is demonstrated, and the method and process of effect experiment about Low Noise Amplifier and Limiter are also explained. The experimental system is established, and the system is composed of low power microwave source such as TWT, test equipment for obtaining the effect parameters, and some of auxiliary equipments as camera, optical microscope or electron microscopy, attenuator, detector, and directional coupler etc. The microwave delivered from source is adjusted to the power infused by attenuator, and pour in the decanting point of effecter via directional coupler, then the couple signal created by directional coupler is input to the recording instrument after detecting by detector, finally the power of effecter is obtained. The value of power, which damages the effecter in the microwave pulse environment, is classified at the index of sensitivity, and the threshold is obtained by power diagnose and wave test. Some regular understandings of the HPM effect to electronic device are obtained based on the results of the experiments. It turns out that the index of electronic device is influenced significantly by the energy via front door coupling, the MOSFET made up of GaAs is the most wearing part to HPM in LNA, the damage threshold of LNA is about 40dBm under single pulse while in repetitive pulse the value is from 33.3dBm to 43.9dBm according to different wave band. The damage threshold of Limiter is about 56dBm to80dBm.

Analysis of electrical characteristics and proposal of design guide for ultra-scaled nanoplate vertical FET and 6T-SRAM

This study aims at studying the damage effect of gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) low noise amplifier (LNA) with repetitive high-power microwave (HPM) pulses. The theoretical function for the thermal accumulation effect is derived, which depends on the pulsewidth, the pulse repetition frequency (PRF), and the input power. A simulation model is established to investigate the thermal accumulation effect of repetitive HPM pulses on the HBT. The electric field, current density, and temperature distributions in the HBT with repetitive HPM pulses are discussed first. The influence of the repetitive HPM pulse parameters on the thermal accumulation effect is studied by theoretical analyses and simulations. Results show that the thermal recovery time increases with the pulsewidth or the input power increases. In addition, it is concluded that the frequency does not affect the thermal recovery time. The simulation results agree with the theoretical results. Finally, the damage effect of repetitive HPM pulses is experimentally verified.

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">NA</i> ), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.

TCAD simulations of FDSOI devices down to deep cryogenic temperature

According to most recent 2004 International Technology Roadmap for Semiconductor (2004 ITRS), the high performance (HP) MOSFET physical gate length will be scaled to 9nm (22nm technology node) in 2016. We investigate the manufacturability of this sub-10nm gate length fully depleted SOI MOSFET by TCAD simulation. The commercial device simulator ISE TCAD is used. While it is impractical for experiments currently, this study can be used to project performance goals for aggressively scaled devices. In this paper, we will optimize different structure and process parameters at this gate length, such as body thickness, oxide thickness, spacer width, source/drain doping concentration, source/drain doping abruptness, channel doping concentration etc. The sensitivity of device electrical parameters, such as Ion, Ioff, DIBL, Sub-threshold Swing, threshold voltage, trans-conductance etc, to physical variations will be considered. The main objective of this study is to identify the key design issues for sub-10nm gate length Silicon based fully depleted MOSFET at the end of the ITRS. The paper will present the final optimized device structure and optimized performance will be reported.

An improved structure of silicon carbide metal-semiconductor field-effect transistors (MESFET) is proposed for high power microwave applications.Numerical models for the physical and electrical mechanisms of the device are presented,and the static and dynamic electrical performances are analysed.By comparison with the conventional structure,the proposed structure exhibits a superior frequency response while possessing better DC characteristics.A p-type spacer layer,inserted between the oxide and the channel,is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge.Meanwhile,a lightly doped n-type buffer layer under the gate reduces depletion in the channel,resulting in an increase in the output current and a reduction in the gate-capacitance.The structural parameter dependences of the device performance are discussed,and an optimized design is obtained.The results show that the maximum saturation current density of 325 mA/mm is yielded,compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET,leading to an increase of 79% in the output power density.In addition,improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET,respectively.

The back-door coupling effects of the low noise amplifier (LNA) under high power microwave (HPM) has been studied in this paper. First, a low noise amplifier is designed by the circuit simulation software Advanced Design System (ADS), then the LNA circuit is imported in to the High Frequency Simulator Structure (HFSS) to carry out the hybrid analysis of back-door coupling effects of HPM on LNA. We get the voltage of the gate and drain terminals of the LNA transistor. After that, the voltage is regarded as an interference signal, and is added to the transistor's corresponding pin, which is simulated by ADS. All above operations are aimed at comparing the changes in gain and noise figure before and after adding the interference signal to the LNA. At last, it is concluded that special protection should be put on signal input pins, and this can be used as a guide to provide protection to the LNA from back door coupling of high power microwave in application.

Self-heating effects limit the performance of high-power AlGaN/GaN HFETs. Knowledge of the temperature in the active area of AlGaN/GaN HFETs is essential for optimizing device design, performance and reliability, however, direct measurement of this temperature is not readily achieved by IR techniques. Improved temperature information can be obtained by micro-Raman spectroscopy allowing temperature measurements with 1 /spl mu/m spatial resolution, important for local device geometries in the micron/sub-micron dimension range. This novel approach allows fast temperature measurements with minimal influence on device performance. We illustrate the use of micro-Raman spectroscopy for thermal management and device failure assessment by studying effects of device design and substrate on temperature in active high-power AlGaN/GaN HFETs. Temperature evolution up to device failure was investigated.