Abstract
To preserve the SystemC semantics under parallel discrete event simulation, a compiler based approach statically analyzes race conditions in the design model. However, there are severe restrictions: the source code for the input design must be available in one file, which does not scale. This disables the use of intellectual property (IP) and hierarchical file structures. This paper scales the static analysis design flow to support separate files and IP reuse by introducing partial segment graph and partial port mapping abstractions and prevent IP security leakage. Experiments demonstrate the effective design flow and sustained speedup with parallel IPs.
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