Abstract

The high flexibility of FPGAs predestines them for emulation and prototyping of ASIC designs. To increase the available amount of resources or to reduce costs, multiple low cost mainstream FPGA boards can be combined into one cluster. This paper presents a new algorithm for the distribution of application tasks into a cluster of FPGAs. This algorithm focuses on both clustering and mapping in one single step, which can be split into two phases. The first phase uses load balancing techniques, to achieve scalability for the number of tasks in the application and the number of FPGAs in the cluster. In the second phase different heuristic search techniques are used, to solve optimization problems, like the reduction of the maximum dilation and the maximum capacity utilization. In order to be applicable to many different topologies, the algorithm supports heterogeneous and irregular structures for FPGA clusters.

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