Abstract
We experimentally show vertically stacked, multi-layer, low-temperature deposited photonics for integration on processed microelectronics. Waveguides, microrings, and crossings are fabricated out of 400°C PECVD Si3N4 and SiO2 in a two layer configuration. Waveguide losses of ~1 dB/cm in the L-band are demonstrated using standard processing and without post-deposition annealing, along with vertically separated intersections showing -0.04 ± 0.002 dB/cross. Finally 3D drop rings are shown with 25 GHz channels and 24 dB extinction ratio.
Highlights
Advances in silicon and silicon-compatible photonics have spurred intense research in the area of optical interconnects, where it could potentially be used to increase the bandwidth and lower the power of computing systems such as multi- and many-core processors [1,2]
L2, the second photonic layer begins above the microring resonator and extends to the output facet, where light can be coupled out to read the drop port
We have demonstrated here a process for integrating multiple photonic layers on the backend of Complimentary Metal-Oxide-Semiconductor (CMOS) electronics
Summary
Advances in silicon and silicon-compatible photonics have spurred intense research in the area of optical interconnects, where it could potentially be used to increase the bandwidth and lower the power of computing systems such as multi- and many-core processors [1,2]. This approach limits photonics to a single layer. In addition using this c-Si for both electronics and photonics is problematic since photonics requires a thick oxide layer (typically a few micrometers) underneath for optical isolation while SOI electronics requires a small layer of only tens to a few hundred nanometers in order to ensure thermal flow from the devices to the substrate. Research groups, including ours have shown that this layer can be repurposed for optics [9,10], generally at the cost of more real estate and with some modification of standard fabrication
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