Abstract
This paper presents the sampling and comparator speed-enhancement techniques for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor limiting the sample speed under ultra-low voltages. Delayed cross-coupling comparator is introduced in this work, which enhances the comparator regeneration while keeping the noise comparable. A 0.35V 8b 12MS/s SAR ADC is designed in a 65nm CMOS technology to prove the proposed techniques. The post-layout simulated SAR ADC consumes only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.71~\mu \text{W}$ </tex-math></inline-formula> and achieves SNDR of 48.8dB at Nyquist input, resulting in a figure-of-merit (FoM) of 2.47 fJ/convertion-step. Simulation results show the proposed speed-enhancement techniques improve the sampling rate of SAR ADC significantly under near-threshold supply voltages.
Highlights
W ITH the scaling down of feature sizes in advanced CMOS technologies, the standard supply voltages are getting lower
Working at low power supply voltage, successive approximation register (SAR) analog-to-digital converters (ADC) have a wide range of applications in wireless sensor network, biomedical (EEG, ECG, EMG), environmental monitoring and other fields
It is composed of a split capacitor array [7], two sampling switches with the proposed level-shifted clock boosting circuits, the proposed delayed cross-coupling comparator and control logics
Summary
W ITH the scaling down of feature sizes in advanced CMOS technologies, the standard supply voltages are getting lower. The control signal can be adjusted manually in the simulation When this value is set larger, the delay time is shorter, and the comparator is faster but noise performance gets worse. When this value is set small, the rising edge of clk arrives later, and the comparator’s noise is reduced but the speed is limited. After a lot of simulations and comparisons, when the control voltage is set to 185mV, the optimal delay time on clk is 1.86ns, and the speed and noise performance of delayed cross-coupling comparator are optimized. Simulation results show the proposed comparator achieves similar power with NP-latch comparator, but the noise of the proposed one is much lower
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