Abstract

The industry trend of Chip Multiprocessors (CMPs) architecture is to move from 2D CMPs to 3D CMPs architecture for obtain higher performance, more reliability, and reduced memory access latency. However, one key challenge in designing the 3D CMPs is the thermal issue as a result of maximizing the throughput . Therefore, applying Runtime Thermal Management (RTM) has become crucial for controlling thermal hotspots. In this thesis, two methods of run-time task migration are presented to balance the temperature and reduce the number of hotspots in 3D CMPs. The proposed techniques consider hotspots both in the core and the memory layers simultaneously to make the optimum run-time task migration decisions. The first proposed approach is divided into two algorithms working in parallel, which aim at maximizing the throughput on the 3D CMPs while satisfying the peak temperature constraints. Experimental results show that the proposed architecture yields up to 60% reduction in overall chip energy. The proposed architecture improves the IPC for canneal and fluidanimate applications by 18% and 14%, respectively. In the second method, the proposed technique migrates the hottest core with the optimal coldest core instead of the coldest core in the core layer. The optimal coldest core is selected by considering hotspots.

Highlights

  • With the advanced of transistor technologies, processors have become very advanced and complicated since 2005 [49]

  • As shown in this figure, the proposed method ensures that the memory layer of the 3D Chip Multiprocessors (CMPs) is below the maximum temperature of 80°C

  • Experimental results on the PARSEC benchmarks show that the proposed architecture yields up to 60% Energy-Delay Product (EDP), on average, reduction in overall chip energy consumption while the best improvement is recorded with only 72% EDP from the Baseline energy consumption

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Summary

Introduction

RTM becomes necessary to control hotspots and thereby improving the performance of the 3D CMPs. applying the migration technique should consider hotspots both in the core layer and the stacked memory layer simultaneously. Applying the migration technique should consider hotspots both in the core layer and the stacked memory layer simultaneously This can prevent to cause the emergence of new hotspots. A new run-time task migration technique is being proposed in this chapter to control temperature variances both in the core layer and the memory layer simultaneously in order to make the optimum task migration decisions more efficiently. The proposed technique aims to achieve balanced hotspots and temperature variations on the 3D CMPs. it is crucial that the system must select the optimal coldest core to be migrated with the hottest core in the core layer rather than selecting the coldest core.

Overview In this section, we introduce the recent major problems in the area of 3D CMPs
Thesis Contributions
Thesis Organization
Thermal Problem and Power Wall
Multiprocessor to Many Core Processor Extension
Memory Gap and Bandwidth Wall
On-Chip Memory
Heterogenous On-Chip Architecture
Two to the Three-Dimensional CMPs
Trends on Power Aware CMPs
Dynamic Voltage Frequency Scaling
Task Migration
Chapter Summary
Clock Gating
Task Scheduling
Interconnection Thermal Management
The Target System Architecture
The Proposed Method
The Task Migration Technique in the Memory Layer
The Experimental Evaluation
The Platform Setup
The Proposed Technique
Measuring the Cores' Temperature and the DRAM Banks' Accesses
Finding Hotspots and Cold Spots in both Layers
Finding the Optimal Coldest Core
Proceeding the Migration
Thesis Summary
Thesis Conclusions
Findings
Future Work
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