Robust design of HV pLDMOS-ESCR structures in a 60-V BCD process

Abstract

A pMOS transistor can be used as an electrostatic discharge (ESD) protection device; however, due to its higher turn-on resistance, it has a poor ESD robustness than that of nMOS transistors. Nevertheless, for a high-voltage (HV) p-channel laterally-diffused MOS (pLDMOS), which has a low impact-ionization rate, almost a non-snapback phenomenon (high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</sub> value) and then with a high latch-up (LU) immunity. What is happening if a pLDMOS embedded with an HV silicon-controlled rectifier (ESCR)? In this paper, a novel HV pLDMOS-ESCR is proposed by implanted an extra N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> diffusion region in the drain-side among a pLDMOS. Meanwhile, the location of the N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> diffusion region is changed in order to investigate the impact on ESD capability. And, in this work, three different unit finger widths will be evaluated. Eventually, the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t2</sub> value of “pnp”-type among HV pMOS-ESCR will be four times higher than that of “npn”-type at least, in the same time, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</sub> value of “pnp”-type HVpMOS-ESCR higher than that of “npn”-type, too. Therefore, the “pnp”-type HV pLDMOS-ESCR structure is an excellent structure in the HV technology due to its high ESD and latch-up immunities.