Abstract
We present a low power radio frequency interference (RFI) mitigating receiver back-end application specific integrated circuit (ASIC). The ASIC includes an on-chip analog to digital converter (ADC) and a RFI detecting/mitigating digital signal processing (DSP) block. The ASIC is capable of processing signals with bandwidths exceeding 1.0GHz. The ADC has a 10-bit, 2 GS/s radiation-hard successive approximation register (SAR) architecture. The DSP block includes a 1024-channel polyphase filter bank (PFB), a fast fourier transform (FFT) blocks and Kurtosis detection & accumulation block. The total power consumed is less than 190mW, including both ADC and DSP. The DSP will have a high degree of programmability that includes the selection/bypassing of the Kurtosis estimation, selection of the number of channels, selection of the decimation factor and selection of time spans for the accumulation of statistical averages.
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