Abstract
The proposed article introduces integrated receiver to using 0.18um CMOS technology. The proposed integrated receiver consists of low noise amplifier (LNA), double balance mixer, balanced voltage-controlled oscillator (VCO), common-gate transmitting amplifier (TA) with low-pass filter, band-pass Gm-C filter, and 10-bit 40MS/s pipelined analog to digital converter (ADC) with subsampling technology. The presented low-pass ladder filter by using bilinear transform to a fifth order performance eliminates redundant switches by sharing technique, both dynamic range scaling and minimum capacitor scaling. The proposed 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order loop bandpass filter uses Gm-C cell to support two-stage circuit of common-gate transmitting amplifier (TA). The presented 10-bit 40-MS/s pipelined ADC, which low power dissipation is obtained by employing the amplifier sharing and SHA-less architecture is eliminated.
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