RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate

Abstract

In this paper, we investigate the impact of a passivation layer on the performance of a commercial high-resistivity (HR) SOI CMOS technology. The passivation layer consists of a 300-nm-thick polysilicon cover located directly below the buried oxide (BOX). Both passive and active devices are studied. It is demonstrated that substrate passivation completely suppresses substrate losses that are usually induced by parasitic surface conduction at the substrate/BOX interface in oxidized HR Si substrates. We also report no effect of the underlying polysilicon on the dc and RF behavior of MOSFETs devices. The results shown here strongly suggest that substrate passivation using polysilicon is a promising tool to eradicate substrate losses in HR SOI wafers, thereby increasing the performance of functional SOI logic and high-speed circuits.