Abstract
AbstractPower consumption and speed of computing systems depend on their arithmetic modules such as adder, subtractor, and multiplier. So, the need for high speed, error tolerance, and power efficiency nature of few applications has been improved by developing approximate adders. Increasing the effectiveness of integrated circuits by making the trade-off between accuracy and cost has got significant importance. A systematic methodology for optimizing the architecture of approximate adders has been proposed and called optimized lower part constant-OR adder (LOCA). In this article, the approximate adders are designed by redesigning its logic circuit, implemented on reconfigurable architectures, and then compared with traditional adder architectures. The proposed architecture outperforms its contemporary architectures in terms of hardware and accuracy.KeywordsApproximationStochastic computingError metricsHardware trade-off
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: Sustainable Communication Networks and Application (Proceedings of ICSCN 2021)
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
