Retention test and electrical stress correlation to anticipate EEPROM tunnel oxide reliability issues

Abstract

This paper shows how floating gate memory cells behavior during retention tests can be predicted relying on static stress tests. The electric high-field induced during Write/Erase cycles is mainly responsible for the retention time degradation because it creates intrinsic failures or traps in the EEPROM tunnel oxide [1][2]. EEPROM retention degradation due to the oxide quality impacts directly the EEPROM threshold voltage (V T ) distribution by creating extrinsic populations. Indeed, post cycling retention tests [3] show a large tail of bits which erase faster than typical bits. Retention is the length of time an EEPROM can reliably retain data. This test is very useful to screen out defective cells but induces significant test time overhead. To overcome this limitation, a new technique based on stress tests is used to anticipate retention test results.