Abstract
Estimation of resistance of power devices has become critical for improving the efficiency of on-chip power-management circuits. In this paper, we present an efficient technique for estimation of resistance of a large lateral power-array layout along with parasitics. We extract a resistive network for metalizations utilizing the finite-element method. The method primarily benefits in terms of computational speed from reuse methodology facilitated by repetitive structure of the metal interconnect layers. Device channels are modeled by linear resistances as the power MOS operates mostly in the linear region. Since we avoid use of heuristic-based lumped models or extrapolation techniques for resistance modeling, a good level of accuracy is achieved.
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