Residue checker using optimal signed-digit adder tree for error detection of arithmetic circuits

Abstract

In this paper, a new residue checker using optimal signed-digit (SD) adder tree structure is presented for the error detection of multiply-accumulate arithmetic circuit. The modulus of the redisue cheker is set to m = 2P + u, where n ∊ {− 1,1} and p is the word length of the residue checker. By switching u = 1 to/from u = − 1, more 2-bit errors can be detected using the same checking circuit. The fast modulo m SD adder with an end-around carry is introduced, so that the modulo m addition time is independent of the word length of operands of the residue checker, and the delay time of the proposed residue checker is dependent of the stages of the binary tree structure of the modulo m SD adders. When n is the word length of the operands of the multiply-accumulate circuit, we can obtain an optimal binary tree structure with the shortest path of SD adders, in which there are log2 n + log2(n/p) + l stages of SD adders. We also implement the residue checker circuts with different p for n = 32 and n = 64 and the best one is with p = 8 both in delay time and error detection.