Research on the effect of single-event transient of an on-chip linear voltage regulator fabricated on 130 nm commercial CMOS technology

Abstract

We report single-event transient (SET) responses of an on-chip linear voltage regulator in 130nm commercial standard CMOS technology by heavy ion experiments at first. Responses can be distinguished by the load current. When the light load current was applied, the negative SET on the output of the regulator larger than 200mV was not observed, while the positive SETs that are larger than 400mV and last for about 200ns were observed. By comparison, when the heavy load current was applied, both positive and negative SETs that are larger than 400mV and last for several hundred ns were observed. Next, the mechanism behind the phenomenon is analysed and then verified by the post-layout SPICE circuit simulation. It is demonstrated that the input voltage, load current and the load capacitance are key elements in determining the severity of SET. Finally, the most sensitive node is located by analysis and SPICE circuit simulation, which lies in the output of the amplifier inside of the bandgap reference (BGR). This result is a primary consideration in the development of the hardening technique.