Research on metal contamination in process lines of superconducting quantum processor chips

Due to an increasing demand of developing III-nitride optoelectronics on silicon substrates, it is necessary to compare the growth and optical properties of III-nitride optoelectronics such as InGaN based light emitting diodes (LEDs) on silicon substrates and widely used sapphire substrates. GaN-on-silicon suffers from tensile strain, while GaN-on-sapphire exhibits compressive strain. This paper presents a comparative study of InGaN/GaN multiple quantum wells (MQWs) grown on a silicon substrate and a sapphire substrate under identical conditions. It has been found that GaN strain status has a significant influence on the growth and the optical properties of InGaN/GaN MQWs. Photoluminescence measurements indicate the InGaN/GaN MQWs grown on a silicon substrate exhibit significantly longer wavelength emission than those on a sapphire substrate. Detailed x-ray diffraction measurements including reciprocal space mapping measurements confirm that both indium content and growth rate in the InGaN MQWs on the silicon substrate are enhanced due to the tensile strain of the GaN underneath compared with those on the sapphire substrate. This work also presents an investigation on strain evolution during the InGaN MQWs growth on the two different kinds of substrates. A qualitative study based on in-situ curvature measurements indicates that a strain change on the silicon substrate is much more sensitive to a growth temperature change than that on the sapphire substrate. It is worth highlighting that the results provide useful guidance for optimising growth conditions for III-nitrides optoelectronics on silicon substrates.

Superconducting quantum circuits (SQCs), composed of superconducting capacitors, inductances, Josephson junctions, and transmission lines, exhibit macroscopic quantum effects at ultra-low temperatures. Due to the extremely low dissipation of superconductors, an important application of SQCs is superconducting qubits with long coherence time. Quantum computing based on superconducting qubits is a leading physical realization method of quantum computing, which is theoretically capable of accelerating many computational problems including quantum simulation, database searching, and optimization. In the long run, to use the power of quantum computing to its full extent, universal quantum computers should be constructed with quantum error correction. In the short term, one of the most pressing targets of the superconducting quantum computing community is to demonstrate quantum advantage using noisy intermediate-scale quantum chips. Both goals rely on the increasing of the number of coupled qubits in a quantum circuit and the quality of these qubits, which dictate the breadth and the depth of a problem it can solve, respectively. The fabrication of SQCs has adopted a few manufacturing processes from conventional integrated circuits. Quantum chips containing multiple superconducting qubits can be made and packaged on a large scale. “Quantum supremacy” has been demonstrated on a quantum chip with fifty-three qubits fabricated using the flip-chip bonding technology. However, to demonstrate quantum advantage, the quality and quantity of qubits need to increase simultaneously. Dissipative channels emerge in circuit design, material preparation, chip fabrication, and working environment, limiting the lifetime of superconducting qubits. For quantum chips with tens to hundreds of qubits, the integration will also introduce extra processing steps which may degrade the qubits, and unwanted coupling to loss channels. Most of these channels are microscopically related to materials constructing the quantum chips, chip surfaces, and material interfaces. Thus, it is important to investigate the material growth and device fabrication of SQCs, and to understand the material related loss mechanisms. This review paper investigates the material related topics in superconducting quantum circuits pertinent to the quantum computing application from a comprehensive perspective. The history of SQCs is briefly mentioned, followed by the peculiar characteristics as an engineerable quantum system, and a roadmap to quantum advantage and universal quantum computing in the next a few years. Technically, the superconducting quantum computer is compared to a Schrodinger’s cat, and can be boiled down into three parts, i.e., quantum chips, the environment, and the operating system, corresponding to the cat, the box, and the observer, respectively. The material related decoherence channels of the SQCs can be sorted into four categories; each will be discussed in details. To fabricate SQCs with minimal loss, the processing technologies are elaborated, including qubit design, material selection, surface treatments, film growth, and Josephson junction, etc. Though there are general guidelines that amorphous materials should be avoided and processing induced damage should be minimized, more is to be investigated due to the emerging of new materials and new fabrication methods. The last part presents the potential application of the superconducting quantum computer and its current state of play. SQC for quantum computing is a multi-discipline research topic, demanding joint efforts from different scientific and technical areas. Materials science and device processing will play important roles along the way to quantum practicality.

Abstract: The rapid advancement of quantum computing is largely driven by innovations in quantum chip architectures, with superconducting and topological qubits emerging as the most promising candidates for scalable and fault-tolerant quantum processors. Superconducting qubits, built using Josephson junctions, have demonstrated significant progress in coherence time, gate fidelity, and quantum error correction, making them the backbone of leading quantum processors such as IBM’s Eagle and Google’s Sycamore. Meanwhile, topological qubits, based on Majorana zero modes (MZMs) and non-Abelian anyons, offer intrinsic error resistance, reducing the computational overhead required for fault-tolerant quantum operations. This chapter explores the fundamental principles, fabrication techniques, and scalability challenges associated with these next-generation quantum chips, highlighting key advancements in hybrid quantum architectures, quantum error mitigation, and cryogenic quantum-classical interfacing. Additionally, it examines the geopolitical and ethical considerations of quantum supremacy, along with the transformative impact of next-gen quantum chips on AI, cryptography, materials science, and optimization problems. As research accelerates, the path toward scalable, fault-tolerant quantum computing is becoming clearer, paving the way for a future where quantum processors outperform classical supercomputers in solving the world’s most complex challenges. Keywords: Quantum chips, superconducting qubits, topological qubits, Josephson junctions, Majorana zero modes, quantum error correction, hybrid quantum architectures, fault-tolerant quantum computing, cryogenic electronics, quantum-classical interfacing, scalable quantum processors, AI-driven quantum computing, quantum supremacy, post-quantum cryptography, nanofabrication, quantum hardware innovation

This paper examines the DC performance of Dual-Gate MISHEMT with different substrate material such as sapphire, silicon carbide SiC, and silicon. The performance parameters evaluated are threshold voltage, drain current, transconductance, and drain conductance. It is observed that DG-MISHEMT with the sapphire substrate and HfO2 gate dielectric results in positive threshold voltage shift from −4.7 to −3.8 V(∼19%) and also degrades the drain current as compared to the device with silicon nitride gate dielectric due to the reduced channel charge concentration. But the device with HfO2/Al2O3 gate stack maintains 182 mA/mm of IDS along with a positive threshold voltage shift of 14.8% as compared to DG-MISHEMT with Si3N4 gate dielectric and sapphire substrate. A similar performance has been observed with Dual-Gate MISHEMT with SiC and silicon substrate. The device, having the silicon substrate and HfO2/Al2O3 gate stack, shows a positive threshold voltage shift of ∼53%, but as a trade-off the drain current reduces to 158 mA/mm as compared to 183 mA/mm of the device at low drain bias with the sapphire substrate and Si3N4 gate dielectric.

As the pixel size in CMOS image-sensor has scaled down less than 1 μm, photo sensitivity which is a ratio of photo and dark current has been important. To improve photo sensitivity in CMOS image-sensor, the achievement of lower dark current is essential. Leakage current is influenced by crystallographic, trapped charge at the SiO2/Si interface, structural defects, and especially metallic contaminant impurities. Also, these contaminant impurities degrade the minority-carrier recombination lifetime. Thus, we investigated the dependency of the properties of CMOS image-sensor on metallic contamination. Standard aqueous solutions of metallic ion were dropped on the surface of silicon wafers and the wafers were spin dry. They were heated to drive the metallic ion contaminants into the silicon bulk. After that, we fabricated 4-Tr CMOS image-sensor cells. In silicon bulk wafer, the minority-carrier recombination lifetime decreased with increasing a metallic contaminant concentration. These contaminations result in degradation of dark current, sensitivity of photodiode and sensing margin of CMOS image-sensor. These results indicate that metallic contaminants are critical for increasing dark current because metallic contaminants remain inside the photo-diode region, ~3 μm. In our study, we applied a proximity relaxation-type gettering method. We formed the nano-cavities close to the depletion region using hydrogen ion implantation, as shown in Fig 1. These cavities getter metallic impurities on the cavities wall. Sensing margin of CMOS image-sensor implanted by hydrogen ion was dramatically improved, as shown in Fig 2. In addition, although metallic contaminant concentration increased, the device performances of CMOS image-sensor were constant compare with that of bulk wafer which were not implanted (Fig. 3). These results indicates that proximity gettering by using hydrogen ion implantation was effective in metal gettering for image-sensor. We investigated the correlation of metallic contaminant and sensing margin of CMOS image-sensor. Finally, we will suggest an extremely proximity gettering method for removing metallic contaminants of CMOS image-sensor.* This work was financially supported by the Brain Korea 21 Plus Program in 2013 and SiWEDS (Silicon Wafer Engineering and Defect Science).

Enhancement of ZnO nucleation in ZnO epitaxy by atomic layer epitaxy

Electrophysical parameter comparison of 2DEG in AlGaN/GaN heterostructures grown by the NH3-MBE technique on sapphire and silicon substrates

Ammonia molecular-beam epitaxy has been used to grow gallium nitride (GaN) transistor heterostructures on sapphire and silicon substrates. GaN transistors with a 1.2-mm periphery fabricated on substrates of both types exhibited similar high static characteristics: saturation current density above 0.75 A/mm, transconductance above 300 mS/mm, and breakdown voltage above 120 V. Measurements of the small-signal parameters showed that transistors based on silicon substrates possessed high gain in a frequency range up to 5 GHz; the specific output power at 1 GHz amounted to 5 W/mm for transistors on sapphire substrate and 2 W/mm for transistors on silicon substrate.

The photoluminescence properties of undoped & Eu-doped ZnO thin films grown by RF sputtering on sapphire and silicon substrates

We investigated the efficiency droop and polarization-induced internal electric field of InGaN blue light-emitting diodes (LEDs) grown on silicon(111) and c-plane sapphire substrates. The efficiency droop of the LED sample grown on silicon substrates was considerably lower than that of the identically fabricated LED sample grown on sapphire substrates. Consequently, the LED on silicon showed higher efficiency at a sufficiently high injection current despite the lower peak efficiency caused by the poorer crystal quality. The reduced efficiency droop for the LED on silicon was attributed to its lower internal electric field, which was confirmed by reverse-bias electro-reflectance measurements and numerical simulations. The internal electric field of the multiple quantum wells (MQWs) on silicon was found to be reduced by more than 40% compared to that of the MQWs on sapphire, which resulted in a more homogenous carrier distribution in InGaN MQWs, lower Auger recombination rates, and consequently reduced efficiency droop for the LEDs grown on the silicon substrates. Owing to its greatly reduced efficiency droop, the InGaN blue LED on silicon substrates is expected to be a good cost effective solution for future lighting technology.

We investigate the strain difference in InGaN/GaN multiple quantum wells of blue light-emitting diode (LED) structures grown on silicon(1 11) and c-plane sapphire substrates by comparing the strength of piezo-electric fields in MQWs. The piezo-electric fields for two LED samples grown on silicon and sapphire substrates are measured by using the reverse-bias electro-reflectance (ER) spectroscopy. The flat-band voltage is obtained by measuring the applied reverse bias voltage that induces a phase inversion in the ER spectra, which is used to calculate the strength of piezo-electric fields. The piezo-electric field is determined to be 1.36 MV/cm for the LED on silicon substrate and 1.83 MV/cm for the LED on sapphire substrate. The ER measurement results indicate that the strain-induced piezo-electric field is greatly reduced in the LED grown on silicon substrates consistent with previous strain measurement results by micro-Raman spectroscopy and high-resolution transmission electron microscopy.

The InGaN/GaN multiple quantum wells (MQWs) light emitting diodes (LEDs) were grown by metalorganic chemical vapor deposition (MOCVD) on silicon and sapphire substrates, respectively. The Optical and crystal properties of InGaN/GaN MQWs LEDs were investigated by room temperature photoluminescence (PL), temperature dependent PL measurements, Raman spectra and high-resolution double crystal X-ray diffraction(DCXRD). These results indicate that the crystal quality of InGaN/GaN MQWs growth on sapphire substrate are more preferable than that of InGaN/GaN MQWs growth on silicon substrate, and the interface of MQWs growth on substrate or silicon substrate is level. The peak positions of InGaN/GaN MQWs are 2.78 eV (446nm) and 2.64 eV (468.8nm) growth on sapphire substrate and silicon substrate, respectively.

Raman characterization and stress analysis of AlN:Er3+ epilayers grown on sapphire and silicon substrates

Hysteresis loops in the emissivity of VO2 thin films grown on sapphire and silicon substrates by a pulsed laser deposition process are experimentally measured through the thermal-wave resonant cavity technique. Remarkable variations of about 43% are observed in the emissivity of both VO2 films, within their insulator-to-metal and metal-to-insulator transitions. It is shown that: i) The principal hysteresis width (maximum slope) in the VO2 emissivity of the VO2 + silicon sample is around 3 times higher (lower) than the corresponding one of the VO2 + sapphire sample. VO2 synthesized on silicon thus exhibits a wider principal hysteresis loop with slower MIT than VO2 on sapphire, as a result of the significant differences on the VO2 film microstructures induced by the silicon or sapphire substrates. ii) The hysteresis width along with the rate of change of the VO2 emissivity in a VO2 + substrate sample can be tuned with its secondary hysteresis loop. iii) VO2 samples can be used to build a radiative thermal diode able to operate with a rectification factor as high as 87%, when the temperature difference of its two terminals is around 17 °C. This record-breaking rectification constitutes the highest one reported in literature, for a relatively small temperature change of diode terminals.

MOCVD (metalorganic chemical vapor deposition) of GaN on both silicon and sapphire substrates was studied over the temperature range of 370 to 1050° C. The crystallinity and surface morphology of the films varied with the deposition temperatures. By first depositing an AlN buffer layer, the crystallinity of GaN was improved for low temperature depositions, but little improvement in the surface morphology was observed. On sapphire (0001) substrates, epitaxial layers were produced at a deposition temperature as low as 500° C. With silicon substrates, polycrystalline films were produced which were randomly oriented on the (111) plane and highly oriented on the (100) plane. The surfaces of the films were smooth and specular at low deposition temperatures, but degraded at higher temperatures. The energy band gaps of these films are in the vicinity of 3.4 eV, close to where they are expected. Elemental analysis by Auger electron spectroscopy (AES) showed the films to be stoichiometric with low residual impurity concentrations.