Abstract
A new routing method is proposed to reduce the peak far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines on printed circuit boards. The stub uniformly distributed along one of parallel double microstrip lines in the proposed routing method increase the mutual capacitance without much changing the mutual inductance between the aggressor and victim lines. This reduces the difference between the capacitive and inductive couplings and hence the far-end crosstalk. The structure of parallel double microstrip lines is treated as a symmetrical network with 4 ports, simulation on the S parameters is processed. Comparison with the no guard, the serpentine guard, and the via-stitch guard shows the proposed routing method gives the smallest values in the peak far-end crosstalk voltage and has a relatively simpler structure.
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