Abstract
The paper presents two different approaches to optimising operation speed of Programmable Logic Controllers. First approach optimizes architecture of the CPU and the program execution. It shows the two processors bit-byte architecture which support of concurrent execution of bit and byte computation tasks. Second approach bases on hardware implemented control algorithm in reconfigurable platform based on FPGA. In second solution high performance is achieved by fully concurrent hardware execution of algorithm. Specific implementation tools enables typical PLC programming for hardware target platform.
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