Abstract
Abstract With the increasing complexity of system-on-chip designs, the probability of having soft-errors is increasing sharply. Since, adder is one of the essential elements present in almost every digital system, therefore, by making adder fault tolerant will create a potential impact on wide variety of digital applications. In this paper, a review has been presented to demonstrate the previously proposed solutions for fault tolerant adder design. In addition to the self-checking approaches, this paper also presented self-repairing techniques. A comparative analysis in terms of complexity, fault coverage and area-overhead has also been presented to conclude the performance of each covered approach.
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