Reliability response of plasma nitrided gate dielectrics to physical and electrical CET-scaling

Abstract

Here, we investigate the impact of polysilicon predoping and physical gate-dielectric thickness scaling on the interaction of CET, J/sub G/, and TDDB reliability for both NMOS- and PMOS-devices for physical thicknesses between 1.28 nm and 1.58 nm. Furthermore, the impact of an additional N/sub 14//sup +/ ion implantation into the PMOS gate is investigated. For NMOS both modal lifetime and leakage current density are not influenced by changes of the poly-depletion layer thickness or the CET, respectively, that result from increasing P implant dose. Since J/sub G/, scales with physical thickness and since modal lifetime strongly depends upon J/sub G/, both physical thickness and leakage current density can be used to determine the thickness scaling of gate dielectrics reliability. A similar result is found for pMOS though the CET is varied less by the increased B doping level. B penetration resulting in degraded TDDB reliability was observed for the physically thinnest split for excess B doping by p-polySi ion-implantation. An additional N implant into the p-poly proved to prevent pMOS devices from reliability degradation, however, at the expense of any scalability margin that additional B would eventually offer.