Abstract
The reliability of integrated circuits has become an unavoidable subject in the nanoscale era. The susceptibility of combinational logic circuits to faults is of increasing interest, and fast and accurate methods are necessary to take the reliability into account earlier in the design process. As circuits scale to nanometer dimensions, the probability of occurrence of multiple simultaneous faults becomes higher and cannot be neglected anymore. In this work, a signal probability reliability analysis (SPRA) algorithm is presented, allowing an evaluation of the reliability of logic circuits relating to multiple simultaneous faults.
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