Abstract
The reliability of high-speed SiGe:C HBT under electrical stress close to the Safe Operating Area (SOA) limit is analyzed and modeled. A long time stress test, up to 1000h, is performed at bias conditions chosen according to applications targeted for these transistors. During the aging tests, Gummel plots are measured at fixed time to analyze the evolution of base and collector current. At low level injection, we observed an increase of the base current whereas the collector current remains constant for the whole Vbe range and during the 1000h aging time. By means of 2D TCAD simulations, this evolution of base current is attributed to trap activity at the emitter-base junction periphery. Based on TCAD simulation results, we propose an aging law using a differential equation that has been implemented in HiCUM L2 v2.33. This reliability-aware compact model allows designers creating reliability-aware circuit architectures at an early stage of the design procedure, well before real circuits are actually fabricated.
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