Reliability of Chip Scale Packages under Mechanical Shock Loading

Abstract

The reliability of different chip scale packages (CSPs) were studied under mechanical shock loading. The tests were carried out according to the JESD22-B111 standard. An area array with 100-bumps and pre-applied underfill, an area array with 36-bumps (no underfill), and leadless leadframe packages (LLP) with 8- and 48-leads were employed. In addition, the impact of three different printed wiring board (PWB) protective coatings was investigated: Ni(P)|Au, organic soldering preservative (OSP), and Ag on the copper soldering pads. It was found that the smaller package sizes yielded better reliability results than the larger components. In addition, interconnections on Cu|OSP were the most reliable, whereas those on Ag were the least reliable. It is proposed that the dissolved Ag strengthened the solder interconnections, and thus affected the stress levels under mechanical shock loading conditions. The failure modes were different from those commonly observed in drop tested component boards. In this work, the failure mode was cracking of the copper traces leading out of the solder interconnections, and the mode was the same regardless of the component type. The different interconnection geometry and rigidity of the components evoked stress concentrations in the PWB around the components, and thus made the cracks propagate through the copper line of the board instead of the solder interconnections. Furthermore, it was also found out that the die attach interconnection (DAI) underneath the component stiffened the structure and increased stresses in the PWB around the edges of the components. When the die attachment was not soldered, the drops-to-failure doubled with the components having Sn terminal finish, but the failure mode changed as well.