Reliability and wireability optimizations for chip placement on multichip modules

Abstract

The chip placement problem of multichip module (MCM) designs is to map the chips properly to the chip sites on the MCM substrate. Chip placement affects not only the thermal characteristics of an MCM but also routing efficiency, which translates directly into manufacturability, performance, and cost. This paper presents a solution methodology for the optimal placement problem considering both thermal and routing design objectives simultaneously. The coupling is achieved through use of a hybrid-force model that is a combination of the traditional interconnection-force model and a novel thermal-force model. The placement procedure can be used as a design tool to place chips and then determine the tradeoffs which can be made in placing for reliability and wireability. Experiments on five examples including three benchmarks show that the present algorithm yields very high-quality results.