Regenerative feedback repeaters for programmable interconnections

Abstract

FPGA performance is limited mainly by the delay of the programmable interconnection network. This delay increases quadratically with the number of series switches, and is a problem especially when the programmable switches are implemented using MOS transistors, since these have an appreciable resistance and capacitance. The delay can be reduced, at the cost of routability, by limiting the number of series switches per interconnection, or at the cost of area by inserting repeaters. Conventional bidirectional repeaters consist of sets of unidirectional tristate buffers and memory cells. Their benefit is limited due to high area and delay penalty. Area and delay penalty can be alleviated by using a regenerative feedback that senses the beginning of a transition and subsequently enforces it. This requires one buffer and no memory cells. This article shows a network with such repeaters for direction-independent buffering.