Reduction of Stray Capacitance in an Inverter Main Circuit Using Multilayer Printed Circuit Boards

Abstract

This paper deals with stray capacitance in an inverter main circuit on a printed circuit board (PCB), which affects switching characteristics in a voltage source inverter (VSI), and reduction of the stray capacitance. A simulation shows that switching speed is decreased by the stray capacitance on the inverter output electrode pattern. The design guidelines focusing on reduction of the stray capacitance are proposed. Further, based on the guidelines, a SiC-MOSFET VSI to reduce the stray capacitance is designed using a double-sided PCB with 35 μm-thick standard copper foil. Experiments using SiC- MOSFET VSIs show that the inverter with the redesigned PCB shortens the switching time of the drain-source voltage by 10% for the rise time and by 38% for the fall time compared with an inverter based on our previous design guidelines. Hence, the switching loss is also reduced using the redesigned PCB inverter.