Reduction of Power Supply Induced Jitter with Applications to DDR Controllers

Abstract

It is desirable to improve the tradeoff between the power supply induced jitter (PSIJ) performance and the cost for the clock distribution circuit in a double data rate (DDR) controller. This thesis proposes the following techniques to achieve the goal: The static phase offset (SPO) is the dominant mechanism causing reference spurs in the spectrum of the multiplying delay-locked loop (MDLL) output. With a high-gain stage inserted between the phase detector/phase frequency detector and the charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique has been verified at both behavioral level with a Simulink model and the transistor level with circuit simulation results. This thesis also presents a very simple and highly accurate expression for the power supply-induced jitter sensitivity transfer function for CMOS buffer chains. The transfer function is mainly a function of the maximum and minimum propagation delay of the buffer chain. Lastly in this thesis, a concise method is proposed for converting the frequency domain equivalent serial resistance (ESR) and equivalent serial capacitance (ESC) to an approximate broadband equivalent circuit which can be readily used in time domain jitter analysis. Finally a case study demonstrates that, with the proposed techniques in this dissertation, the MDLL based clock distribution circuit for a DDR controller improves the tradeoff between performance and cost compared to the traditional phase locked loop (PLL) based clock distribution circuit.