Reduction of Leakage Power & Noise for DRAM Design Using Sleep Transistor Technique

Abstract

In this paper the analysis of DRAM logic compatible 3T cell has been shown. Due to its high density and low cost of memory, it is universally used by the advanced processor for on chip data and program memory. DRAM has transistor-capacitor cell structure, where capacitor is charged to produce 1 or 0. Memory array, which is arranged in row and column, is word line and bit line respectively. Here I have proposed sleep transistor technique at 3T dram with semantic design, for improvement of leakage and also calculated stability by calculating noise, slew rate and settling time. This circuit proposed two voltage source are connected to bit line and bit line bar respectively. Switching of main transistor is performed by word line, which is at low for write operation and high for read operation. The simulation result shows that when a wide range of operating voltage is taken, which is from 0.7 to 1.3v then it is observed that low voltage operation is suitable for low slew rate or low read access time and the leakage current reduced as increase in the range of operating voltage. At 0.7v the leakage current is 595.4×10-12 amp, slew rate is 6.96×103 dB, noise measurement is 5.995×10-14, settling time is 46.63×10-9. The design has been carried out at the 45 nanometre scale technology on cadence virtuoso simulating tool.