Reduction in Self-Heating Effect of SOI MOSFETs by Three Vertical 4H-SiC Layers in the BOX

Abstract

In this paper a novel structure is proposed for silicon on insulator MOSFETs which improves DC and RF characteristics by three vertical layers of 4H-SiC. Vertical layers are in parallel and extended from silicon drift region toward the substrate through oxide region as heating passageways. These additional layers absorb the heat of active region and transfer to the substrate area. Thus, large value of temperature variation arising from high gate and drain biasing in SOI devices is reduced by applying the proposed structure. It reduced from ~690 K to ~353 K at VG = 10 V. The negative differential resistance is diminished and carriers mobility improved which result in higher and more stable saturation current in comparison with conventional structure. Also, the resultant device has lower delay time. Gate capacitances are approximately equal to the conventional structure but its higher transconductance results in more than 3-times higher cut-off frequency and about 75% improvement in maximum oscillation frequency, at VG = 10 V and VD = 3.5 V. Widespread simulations and comparisons demonstrate that this structure can be considered in high power and RF applications.